Selective signalling system

ABSTRACT

The disclosure relates to a central station having an encoder which is operable to selectively call any one of a plurality of individual remote stations by the transmission of a unique code which is comprised of a series of time intervals occupied by the presence or absence of a signal level. The encoder includes an input such as a keyboard to first develop the particular code to be transmitted in terms of a two-out-of-five bit position representation for each character of the transmitted message. The encoder also includes a register to temporarily store a combination of generated characters and then to automatically add tag and stop characters and translate the composite message into the previously mentioned signal mode for transmission. The encoder circuit transmits a given composite signal at an appropriate time relative to the availability of signalling channels. The code transmitted is of pulses or signals of long length relative to the typical pulse or signal length of noise. Each receiver station includes means for receiving the transmitted composite message, translating such into a code which may be serially decoded in a register decoder set up for serial comparison of each bit of such translated code. The decoder is operated to progressively and serially compare each bit of the translated code and advance a bit as long as each received code bit is correct with respect to the assigned station code. The decoder operates to destroy the advancing bit upon the receipt of an incorrect code bit. In the event of the proper code the decoder is made to produce an output in the form of some audible, visual indication or command function. The detector may include a number of parallel decoder paths for a receipt of a plurality of codes each representing a separate command function. The receivers for a given system may be made identical with variations in code assignment being provided by a novel code plug assembly.

United States Patent Edward Camp bowling Harrisburg;

Earl Wilber Eshenauer, .lr., Steelton; Robert Earl Jones, Camp 11111;Michael .Iouph Yaocino, Mecltanicsburg, all 01, Pa.

[72] Inventors [21] Appl. No. 565,624

[22] Filed July 15, 1966 [4S] Patented July 27, 1971 [73] Assignee AMPIncorporated Harrisburg, Pa.

Continuation-impart of application Ser. No. 531,864, Mar. 4, 1966, nowabandoned.

s41 SELECTIVE SIGNALLING SYSTEM 11 Claims, 31 Drawing Figs.

521 user 325/55,

178/l7C,340/168S s11 lnt.Cl noun/o0 50 FieldolSeareh ..32s/s5,s1;

340/l47,157,158,167,l68,174,168 SR, 334, 336, 337; 178/17, 17 A, 17.5

[56] References Cited UNITED STATES PATENTS 2,740,106 3/1956 Phelps325/55 3,292,178 12/1966 Magnuski 325/55 3,335,406 8/1967 Clark 325/553,376,384 4/1968 Achramowicz. 178/175 3,396,239 8/1968 Yamauchi 178/1753,056,116 9/1962 Crane 340/168C 3,175,191 3/1965 Cohn et a1. 325/553,384,873 5/1968 Sharma 325/55 Primary Examiner Robert L. GriffinAssistant Examiner-Albert .1. Mayer KEYBQARD aiii eaaieeeAtromeys-Curtis, Morris and Safford, Marshall M.

l-lolcombe, William Hintze, William J. Keating, Frederick W. Raring,John R. Hopkins, Adrian J. La Rue and Jay L. Seitchik ABSTRACT: Thedisclosure relates to a central station having an encoder which isoperable to selectively call any one of a plurality of individual remotestations by the transmission of a unique code which is comprised of aseries of time intervals occupied by the presence or absence of a signallevel. The encoder includes an input such as a keyboard to first developthe particular code to be transmitted in terms of a two-out-of-five bitposition representation for each character of the transmitted message.The encoder also includes a register to temporarily store a combinationof generated characters and then to automatically add tag and stopcharacters and translate the composite message into the previouslymentioned signal mode for transmission. The encoder circuit transmits agiven composite signal at an appropriate time relative to theavailability of signalling channels. The code transmitted is of pulsesor signals of long length relative to the typical pulse or signal lengthof noise. Each receiver station includes means for receiving thetransmitted composite message, translating such into a code which may beserially decoded in a register decoder set up for serial comparison ofeach bit of such translated code. The decoder is operated toprogressively and serially compare each bit of the translated code andadvance a bit as long as each received code bit is correct with respectto the assigned station code. The decoder operates to destroy theadvancing bit upon the receipt of an incorrect code bit. 1n the event ofthe proper code the decoder is made to produce an output in the form ofsome audible, visual indication or command function. The detector mayinclude a number of parallel decoder paths for a receipt of a pluralityof codes each representing a separate command function. The receiversfor a given system may be made identical with variations in codeassignment being provided by a novel code plug assembly.

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SHEET 5 UF 8 PULSE STRETCHER POWER SUPPLY REGULATED no 60m OUTPUT-1wmume I6 an owl CORE OUTPUT ENCODER OUTPUT T0 TRANSLATOR based on radio,land line or optical transmission. Such uses inlo clude calling, paging,operating and checking equipment function.

With respect to radio communications, one of the most pressing problemsfacing the industry is that of availability of signalling frequencies.Even with careful supervision of those utilizing radio equipment andregulation of the equipment itself, the problem of bandwidth crowdingand interference between signalling channels increases each year.This'means that a selective signalling system must be designed tooperate in as narrow a bandwidth as possible, both with respect to itsuse in existing and standard frequency ranges and with respect to thefew remaining unoccupied bandwidths. With respect to these applicationsthe signalling mode employed in any selective signalling system must besuch that it minimizes inter ference with other intelligence and theassociated signal equipment must be such that the other communicatedintelligence does not interfere with and falsely operate the signallingequipment. In applications over land lines the bandwidth problem ispresent to the same extent as with radio equipment and additionallythere are problems relating to cross talk and amplifier distortion alongthe line. This means that selective signalling mode choices must berelated to signal characteristics other than that of frequency, such asamplitude. The associated signalling equipment must also be chosen tooptimize both signals-to-noise ratio and on-off ratio. In opticalsystems the equivalent of the foregoing problems are all present.

in all of these cases the choice of waveform should be such as to permittransmission and reception with minimum signal degradation anddistortion and the equipment used must provide good discriminationbetween the received waveform and local noise or RFI.

An additional problem present with the imposition of a separateselective signalling system upon existing equipments is one ofcompatibility and power requirement. A large number of two-way radiocommunication .systems exist employed by taxicabs, police, fire and gascompanies. Still other systems exist for use by military and civilianaircraft and for marine use. The typical automobile voltage availabletoday is 12 volts DC and most existing mobile equipments operate fromthis supply. The typical supply aboard ships is some other voltage andusually some other frequency. For portable battery-operated equipmentthe supply may be at another voltage level. A selective signallingsystem for general use should be compatible with all of these systems interms of required power supply or at least in terms of a relativelysimple interface between such supplies ane. such existing equipment.

As still another consideration with respect to signalling the codeutilized should be one which permits an easy implementation of checkingprocedures. Yet another consideration is one of adaptability forinternational use.

As will be appreciated, the foregoing sets forth a wide variety ofapplications wherein a selective signalling system might be expected towork with different types of communication transmitters and receivers.Some of these may be of considerable complexity and sophistication andsome must of necessity be simple and inexpensive.

Accordingly, it is an object of the invention to provide a selectivesignalling system which utilizes a signalling code structure and signalwaveform which reduces the required bandwidth occupied by the systemsignals. It is a further object to provide a selective signalling systemwhich in its implementation is fully compatible, with both complex andsimple radio equipment and with land line and optical transmission andreception equipment. It is a further object to provide a selectivesignalling system which can be used with a large number of transmittersor receivers of substantially identical construction, but with featuresenabling each transmitter or receiver to be easily preset to operatewith a unique calling signal. In conjunction with this last mentionedobject, the system of the invention also contemplates equipment operablewith a code structure which can be readily expanded in terms of numberof transmitter or receiver units. The code structure of the invention issuch as to be acceptable with respect to any language or machine.

It is a final object of the invention to provide a selective signallingsystem including an encoder and one or more decoders of a constructionwhich is reliable and of long life.

The foregoing objectives are attained through the present invention bythe provision of a central station having an encoder which is operableto selectively call any one of a plurality of individual remote stationsby the transmission of a unique code which is comprised of a series oftime intervals occupied by the presence or absence of a signal level.This code is similar to the well-known mark-space coding techniqueemployed in telegraphy. The encoder includes an input means such as akeyboard to first develop the particular code to be transmitted in termsof a two-out-of-five bit position representation for each character ofthe transmitted message. The env coder also includes a register totemporarily store a combination of generated characters and then toautomatically add tag and stop characters and translate the compositemessage into the previously mentioned signal mode for transmission. Theencoder circuit is made to transmit a given composite signal at anappropriate time relative to the availability of signalling channels.The code transmitted is in accordance with the invention made to be ofpulses or signals of long length relative to the typical pulse or signallength of noise.

Each receiver station includes means for receiving the transmittedcomposite message, translating such into a code which may be seriallydecoded in a register decoder set up for serial comparison of each bitof such translated code. In accordance with the invention the decoder ofuse is operated to progressively and serially compare each bit of thetranslated code and advance a bit as long as each received code bit iscorrect with respect to the assigned station code. The decoder operatesto destroy the advancing hit upon the receipt of an incorrect code bit.In the event of the proper code the decoder is made to produce an outputin the form of some audible, visual indication or command function. Tlnaccordance with the invention, in one embodiment the detector mayinclude a number of parallel decoder paths for a receipt of a pluralityof codes each representing a separate command function. The inventionreceivers for a given system may be made identical with variations incode assignment being provided by a novel code plug assembly.

In the drawings:

FIG. 1 is a schematic diagram of the system of the lIlVIIllOIl inadaptations to various transmission media and in adaptations to variouscomponent arrangements;

FIGS. 2A-2C are schematic representations of general encoderembodiments;

FIGS. 3A-3C are schematic representations of general receiverembodiments;

FIG. 4A-4I is a time sequence plot showing the preferred signal waveformused by the invention;

FIGS. 5A and 5B are detailed schematics of a specific embodiment of thesystem encoder;

FIGS. 6 and 7 are schematics showing a preferred decoder wiringarrangement;

FIG. 8 is a partial representation of a magnetic core decoder preferredfor use with the invention;

FIG. 9 is a time sequence plot of the set-clear states employed in thedecoder circuit of FIGS. 6 and 8 to decode a FIG 13 is a detailedembodiment of a preferred decoder circuit; and

FIGS. l4A-E are representative of waveforms to aid in explaining theinvention.

GENERAL DESCRIPTION Relative to the description to follow, the inventionsystem is of the outboard type which embraces a single encoder andtransmitter forming a command station and numerous receivers anddecoders forming receiver stations. Outboard systems are typically usedfor paging. Also contemplated, but not here illustrated, are inboardsystems wherein there are a large number of encoders and transmitterswhich each may generate and send a message identifying the transmitterlocation and indicating the presence of a condition, all received by asingle master receiver. An example of an inboard system is that employedfor city, tire and police call boxes.

Turning now to FIG. 1, there is shown an outboard selective signallingsystem including a variety of transmitter and receiver equipmentsgeneral to the type of application contemplated for the presentinvention. There is included a master encoder capable of generatingstation calling or equipment function codes which are then transmittedby various means such as a radio transmitter, an optical transmitter ora land line transmitter. The master encoder may be operated by manualinsertion of information in digital, decimal or binary form through dialor pushbutton devices or may be machinefed from tape, punch cards orother storage media. The encoded intelligence is then preferablytranslated into a type of on-ofi waveform, to be described hereinafterin detail, which is then transmitted directly or, in many instances,superimposed upon a suitable carrier compatible with the type oftransmission contemplated. For example, with respect to the radiotransmitter, the on-off waveform is superimposed upon a carrier in aselected AM or FM frequency band assigned to the particular type ofcommunication. This may be done directly or by converting the on-ofi"waveform from a DC level or nonlevel into a single frequency tone orabsence of tone or into two tones, one for on and one for offconditions. In the case of optical transmission this waveform isemployed to modulate a transducer capable of biasing an optical sourcesuch as a laser, or like device, into on-off conditions to provide pulsemodulation for that type of transmission. With respect to land linetransmission, the calling code may, in certain instances, be sentdirectly as an on-off voltage level or, as is more frequently the case,sent as a distinct tone or tones in some frequency bandwidth so limitedas not to interfere with voice communication. In closed circuitapplications, such as in factories or as links between pumping stationson gas or oil lines, the calling signal may be superimposed uponexisting communication lines or upon power lines by well-knowntechniques.

As will be developed more fully hereinafter, the code structure andassociated equipment employed by the invention lends itself to use witha relatively large number of called stations or control functions. InFIG. 1, relative to radio transmission, a pair of receivers represent alarge number of possible receiver stations. Each receiver will wherenecessary include equipment to demodulate the transmitted signal and/ordetect the tone or tones used to represent the encoded on-off waveform.With each receiver station there is provided a decoder which has anoutput to some station call device such as an audible or visualindicator. Upon transmission of each calling signal each receiverassociated with the system is actuated to attempt to respond. Only thereceiver decoder set up for the particular code called does, however,respond to produce an output and an indication that the station is beingcalled. All other stations in accordance with the invention do notrespond.

The transmission of an optical calling signal is in a similar fashionreceived by a receiver and its decoder is operated to initiate a stationcall device. In the case of the optical receiver (and applicable to allof the various modes of transmission of FIG. 1) there is shown a pair ofdecoders, which decode the calling signal in parallel. One decoder hasits output connected to initiate some control function. A representativeapplication calling for this arrangement is one where the upper decoderoperates from one calling code to signal the associated station that isbeing called for a normal or working purpose and the lower decoder isset up to receive a special code to initiate some alarm device toindicate the occurrence of an emergency, such as anticipated equipmentfailure or a change of mode of transmission.

The receivers associated with the land line transmission mode are shownto be connected in parallel to represent a .variety of decoderarrangements for station calls, control functions and verification ofreceived call. The lower receiver is set up to supply parallel decoders,one of which has its output connected to a station encoder andtransmitter to verify the successful detection of the calling code bytransmitting a unique code back to a receiver and decoder at the masterstation.

In conjunction with the invention system, a particular type of codestructure and signal waveform is employed. A detailed explanation of itsadvantage to both encoding and decoding equipment as well as totransmission equipment will be made apparent in the detailed descriptionto follow. Briefly, the

' code structure contemplates a translation from decimal members into abinary representation in the encoder, a translation into an on-offwaveform between the encoder and the transmitter and a given receiverand a translation from the on-off waveform into a different binary codefor detection at the receiver decoder. Where necessary the on-offwaveform is translated from a DC level into a tone or tones before beingsupplied to tansmitting equipment and such tone or tones are translatedback into the on-off waveform before being supplied to the detector partof a receiver. The various code forms employed are made to be optimumfor the type of equipment used in each phase of system operation. In thedescription to follow the terms set" and clear" represent the binarysymbols employed in encoding. These terms are used relative toconditions caused in a series of bistable devices in an encoder registerwhich, in the disclosed detailed embodiment, is a specially wiredmagnetic core shift register. When a device is set is will produce anoutput pulse and when it is clear it will produce substantially nooutput pulse.

The terms level (L) and not level (II) hereinafter used relate to thepresence or absence of the code voltage level, or on and off." The L andL terms are also used relative to the decoder operation where L and Epulses are generated from the received waveform. These pulses areemployed to serially drive a decoder register which, in the describeddetailed embodiment, is a magnetic core shift register wired to performthe decode function.

Referring now to FIG. 2A, a command station 10 is shown in a generalschematic diagram to include components to produce and transmit acalling code in the L, I waveform previously mentioned. An input devicesuch as keyboard 12 is provided to enable the selection of calling codethrough pushbuttons representative of numbers I through 9 and 0. Theoutput from 12 is connected to a driver 14, which is made to beresponsive to each pushbutton to inject into an associated register 16,a set-clear pattern in a standard twmout-of-five code representative ofthe particular decimal output from 12. This is shown in the followingschedule with set (S) and clear (C) assigned to five adjacent stages ortime related bit positions.

SCHEDULE Digit Bit Position l C C C S S 2 C C S C S 3 C C S S C 4 C S CC S 5 C S C S C 6 C S S C C 7 S C C C S 8 S C C S C 9 S C S C C O S S CC C In accordance with the invention, register 16 is comprised of aseries of bistable stages adapted to serially store a calling messagecomprised of a number of characters each made up of two set conditionsand three clear conditions in five adjacent stages. FIG. 2 shows 16 tohave 26 stages to accommodate a message comprised of four decimalnumbers, a start and a stop character, with four extra stages. Typicalmessages are shown in FIG. 4 in terms of set and clear states in theregister stages.

After each number is input from 12 to 16 the driver 14 is caused tooperate to shift the 5-bit character from the first five stages to thesecond five stages. For the message length shown (four numbers), afterinput of the fourth number the stages 5-26 of register 16 will be filledby reason of tag start and stop characters caused to be injected beforeand after the first and last bits of the message number in a manner tobe detailed hereinafter.

There is provided a driver 18 which is made responsive to a nonbusycondition of transmitter 20 to cause 14 to drive 16 to output the storedmessage by driving the stages with an oddeven alternating drive. Thisproduces a serial output of set and clear conditions of the stages. Atranslating device shown schematically as a relay 22 is provided totranslate the output from 16 into the on-off waveform previouslymentioned.

The relay 22 includes two coils W1 and W2 which are connected to bealternately operated through a latching contact set cl by input pulsesfrom 16. The coils are chosen such that a pulse through one of the coilswill energize such coil to eventually drive the contact set cl to openthe circuit to such coil and close the circuit for the other coil. Thereis also provided a latching contact set (2 which is driven by both coilsW1 and W2 between a ground contact associated with a L output and acontact from battery Bl associated with an L output.

As mentioned, a set condition will produce a pulse output from 12 and aclear condition will produce substantially no output pulse. With this inmind the message 5371 stored in 16 and comprised of set and clearconditions, as indicated in the top line of FIG. 4, will result in anoutput from 22 to 20 like that shown in the third line of FIG. 4. Thesecond line of FIG. 4 is a time scale made up of 22 millisecondincrements. With the contact set cl positioned as shown, the firstoutput from 16 (the tag set condition producing an L pulse) operates todrive cl to close the path to coil W1 and will operate to close 02 tobattery B1. This produces an L input to 20. The next bit is the firstbit of the first character 5 and is a clear condition. This produces nooutput from 16 and does not operate relay 22. The next bit is a setcondition and thus produces a pulse to coil W1 to drive contact cl to W2and c2 to the ground side of the contact set. The output to 20 will thenbe L. The next bit output is a clear condition which does not operate22. The fourth bit of the character 5 is again a set condition. Coil W2is operated to return cl to call W1 and c2 to battery to produce an Loutput to 20. Following FIG. 4 it will be apparent that th e set-clearpattern stored in 16 will be translated into an L, L waveform whereineach set condition causes a transition from the previous voltagecondition to the alternative condition, L or L.

In accordance with one aspect of the invention, the clock rate or rateof drive pulses supplied to the register 16 is made to be such that theset-clear pattern is output relatively slowly. This produces a waveformcomprised of L and I: conditions which are relatively long in duration.For example, relative to the messages of FIG. 4, the clock rate isadjusted so that each bit from 16 is output every 22 milliseconds. Thismeans that both L andT. conditions will persist at least 22milliseconds. Each character of a message, being comprised of 5-bitpositions, will be 1 milliseconds in length and a four character messagewith l-bit for each tag and stop character will be 462 milliseconds inlength (the stop character not being part Q message length). Therelatively long duration of the L and L conditions is utilized to reduceinterference from RFI and various electrical noise. This is because thetypical noise pattern in either radio or land line transmission iscomprised of bursts of short duration. Accordingly, the rate of messagetransmission is made to be as slow as is practical, considering thenumber of messages per unit of time which must be handled by the system.If the rate is as above outlined a system can handle one call or messageper half second or calls per minute. Normally. it is preferred toprovide a guard band between calls of a length of time a little greaterthan the time length of a character of the message. If this is done thepreviously outlined message length will still permit a calling rategreater than one call per second. This rate is quite sufficient for a10,000 subscriber system. It is, of course, contemplated that for largersystems the message rate may have to be increased, but even with asubstantial increase the pulse rate will be far slower than that of theprior art practice.

As a further aspect, it will be apparent that the messageabove-described is numerically complex in the sense that it includessome 22-bit positions for a single call. This complexity further servesto reduce the likelihood that any combination of spurious pulses willreproduce a given code to cause a station decoder to respond. The codewaveform, being of a single tone of L and Econditions, so compensatesfor the number and length of the code that overall the code of theinvention is still more easily handled than with prior art systems.

The resulting waveform is used to modulate transmitter 20 to effect atransmission of the calling message.

FIG. 2B shows a version of the circuit wherein the outp ut of the laststage of 16 is fed to a standard flip-flop 19 which in one state drivesa tone generator 21 to produce a frequency f, during L conditions and inthe other state merely keys the transmitter 20 to transmit no toneduring I: conditions. Each time a set state is output from 16 theflip-flop reverses its output. FIG. 2C shows another embodiment whereinthe flip-flop 19 drives a tone generator 21 for L conditions and a tonegenerator 23 for L conditions. The two frequencies f and f thenrepresent on and off conditions supplied to 20. As can be appreciatedthe use of but two tones still represents a considerable saving inrequired bandwidth. This latter approach is particularly desirable whenthe transmission mode is single sideband.

FIG. 3A is of a representative receiver station. There is included areceiver 24 to receive and demodulate the message waveform to produce anoutput in the same form as provided from 22 to 20 by the circuit of FIG.2. The output from 24 is fed to 26, schematically shown as a relay,which is connected to a battery B2 to drive a sequence detector 32 withL and L pulses developed in pulse generators 28 and 30. The fourth andfifth lines of FIG. 4 show the on condition of the L and L lines from 26to 28 and 30. The detector includes a serial decoder set up to recognizethe transmitted message and produce an output to some indicator device.

The circuit of FIG. 3A is operated by the waveform of the message 5371of FIG. 4, as follows.

In accordance with the invention the contact set c3 is nor; mally clgsedto ground such that 28 is energized to provide a train of L pulsescontinuously to 32. As will be made apparent, until the first L pulse ininput to 32, the decoder does not respond. When the message input beginsthe first condition is made to be the tag or L-bit. This actuates 26through coil W3 to close 03 to the L path and energize generator 30 toproduce a train of L pulses to 32. The next bit in accordance with thewaveform for 5371 in FIG. 4 is still L and generator 30 is left on longenough to produce tw q pulses to 32.'There is then a transition in thewaveform to L to cause the coil W3 to close c3 to the L path andenergize 28 for a period long enough to produce two L pulses input to32. Next, there is a transition to L for four time periods. Relay 26 isthen operated to energize 30 to provide four L pulses to 32.

FIG. 3B shows a circuit operable with the encoder circuit of FIG. 2B.The received signal is supplied to a filter 25 sensitive to f which inturn drives the coil W3 to cause the operation of generatog 28 and 30dependent upon the presence or absence of L and L conditions or f,. FIG.3C shows the receiver circuit for operation with the encoder circuit ofFIG. 2C. Two filters 25 and 27 separately detect f and f, to directlydrive the generators 28 and 30 to produce L and L inputs to the sequencedetector 32.

As can be discerned from FIG. 4, the input of the waveform results inthe generation of L andT: pulses on separate paths driving 32. If thesepulses are assigned S and C representations a comparison with the codeset into 16 will show that the initial code differs from the final code,which is decoded to provide a detect output. Also for comparison, asecond message 5373 is shown in FIG. 4. This message differs only in thelast character. As will be apparent, the number of bits of the generatedmessage is even, the number of bit positions is even and the start andstop conditions are identical. This permits parity checking proceduresto be easily implemented.

From FIG. 4 it will be observed that the number of bit positionstransmitted is one greater than the number of bit positions decoded.This is inherent in the use of a stop bit which is always the samecondition as the start bit, if the number of bits and bit positions iseven.

This operates to the advantage of automatically restoring the receiverstation to the L condition, which is necessary for system operation asthus described.

In regard to the system as described, various available components maybe employed. The register of the encoder may be a shift register havinga suitable number of stages each comprised of a bistable device such asa relay, tube, transistor or magnetic core. The encoder driver may beany suitable pulse developing device set up to advance intelligencestored in the register and to, on command, clear the register after agiven message has been transmitted. Input from the keyboard may beimplemented by the driver in serial or parallel fashion. The decoder maybe any suitable device set up to operate serially from the type ofpulses produced from the translator 26.

Certain of the control logic required for the foregoing generalembodiment has for simplicity been left to be manually implemented. Inthe description to follow an alternative and more specific embodiment ofthe system of the invention will be detailed, which incorporates anautomatic logic control to carry out the various component operationsautomatically from keyboard input to detect at a receiver station.

In the detailed embodiment to follow the bistable devices employed inthe encoder register and in the receiver decoder are multiaperturecores, one core per stage. The general drive scheme employed is thatknown as MAD-R, described as to a shift register circuit in U.S. Pat.No. 3,125,747. The encoding technique of injecting set-clear patterns tobe described is generally taught in U.S. Application Ser. No. 363,165filed Apr. 28, 1964, now U.S. Pat. No. 3,484,755 in the name of]. P.Sweeney. The decoding technique is generally taught in U.S. applicationSer. No. 444,714 filed Apr. 1, 1965, now U.S. Pat. No. 3,444,532 in thename of Joseph P. Sweeney. Preferred core drivers are generally taughtin U.S. Pat. No. 3,221,176. A specific driver circuit for both theencoding circuit and the decoding circuit is taught in U.S. ApplicationSer. No. 378,652 filed June 29, 1964, now U.S. Pat. No. 3,284,644 in thename ofDormer et al.

DETAILED ENCODER DESCRIPTION Referring now to FIGS. A and 53, analternative and specific encoder circuit 50 is shown, which is capableof auto matically generating the calling message heretofore described asan input to the system transmitter. The circuit is supplied by a powersupply 52, which may be a standard unit capable of developing regulatedDC outputs from a line supply. In the embodiment shown the line supplyis 110", 60 cycles AC and the outputs of 52 are separate DC levels ofabout and 40 volts.

These outputs are connected to the various component circuits of thesystem, including a code input unit 54 which is operable to selectivelyinject an encoded message into a register 56. The unit 54 includes 10switches Kl-K9, and KO operable normally as by a keyboard or by anysuitable transducer to close selected paths to the register 56. Includedin 54 is a lamp LAl in circuit through a current adjusting resistor R1to ground and energized by a transistor Q1 (in FIG. 5B) supplied by the40 supply and 52 through control components to be described hereafter.The base of Q] is connected to be dropped close to ground conditionafter the first character of a message is injected into the register tothus cut off lamp LAl. This indicates to the operator of 54 that amessage is in process. The lamp LAl is held off by the off condition ofQ1 until the complete message has been encoded and transmitted and thecircuit 50 is ready for the next full message to be sent. This isaccomplished by causing the SCR next to O1 to fire after the input ofthe first message character and latch on until the message istransmitted.

Referring back to 54, each of the switches Kl-K9 and KO includes twocontacts such as KlA and K113, as shown relative to Kl. The switches of54 are made such that the upper contacts close before the lowercontacts. Switches of this type are well known. This switch constructionpermits the circuit path associated with the upper contact to be closedand stopped from bouncing before closure of the path associated with thelower contact.

When the upper contact KlA is closed a circuit path is provided leadingfrom the contact to 56 and to windings having set inputs to a selectedtwo of the first five stages of the register. For reasons to be madeapparent, the register 56 includes 26 stages. In the register 56 thefirst ten windings are each associated with one of the numbers 1-9 and0, and each winding links two of the first five stages in patterns likethat given in the schedule previously set forth in the specification.The numbers above the windings in FIG. 5A represent the number of thestages linked by such winding. In the example previously given for themessage 5371 in FIG. 4, the first switch operated links the second andfourth stages to set such, the first, third and fifth stages remainingclear.

In accordance with a preferred embodiment of the system of theinvention, each stage is a multiaperture core (like that to be describedin the detail given as to the preferred decoder embodiment to follow).The register 56 then includes 26 cores. The cores are connected bycoupling loops to provide serial transfer. The first l0 windings shownin FIG. 5A are comprised of set turns N, linking two of the five coresso as to set such cores when the circuit is energized. Additionally, thecores are all linked by advance and prime drive windings for a standardMAD-R, odd-even advance circuit like that detailed in U.S. Pat. No.3,125,747, previously mentioned.

From each of the set windings of 56 the circuit path is commoned to alead connected to the anode of an SCR Q2 in FIG. 5A) which is initiallyin an off state. The cathode of QL. is connected to ground, as shown,and the gate of O2 is connected through a resistor R2 and a capacitor C1back to 54 to the output side of the lower contact of each switch, suchas KIB of K1. Since 02 is initially off, closure of KIA does notenergize the circuit path just described.

The contact KlB has its input side connected in common with the inputside of KIA to the collector of an NPN transistor Q3 having its emitterconnected to ground as shown. Transistor O3 is also initially off. Acapacitor C2 is provided with a charge of nearly 40" from a connectionto the 40" lead from 52 through charge limiting resistor R3. When KllBis closed the lead from C2 (through the path associated with KlB tocharge Cl and R2 to the gate of Q2) goes suddenly from ground to 40".The transient developed thereby couples through Cl and flows through R2to gate Q2 on and cause conduction draining C2. The resulting dischargecauses current flow through the path including contacts KIA, theselected set windings of 56, the common lead of the windings to theanode of O2 to ground. Since the contacts KIA are at this time alreadyclosed, no bounce or transient will be developed due to switch closure,which could adversely affect the setting of the stage selected.

When C2 has substantially discharged, Q2 will cut off due to a lack ofholding current and will remain off due to the back bias developed bythe collapse of the field in inductor L1. The capacitor C2 will rechargethrough charging resistor R3 from the 40 supply lead to 52. The resistorR4 is chosen to keep this supply from holding Q2 on after C2 hasdischarged and to limit the current flow through Q2 during discharge.The inductor L1 and resistor R5 serve to form the pulse produced when C2discharges. Resistor R6 references C1 to ground and resistor R7 is agate ground reference for 02.

All during the operation just described Q3 remains off due to a biassupplied to its base through a resistor R8 from control and timingportions of the circuit. lf Q3 is caused to fire it will keep C2discharged by drawing off the charging current from R3 to ground. If C2cannot charge, then Q2 cannot be gated on and the circuit is effectivelydisabled from setting the register. This control will be explained laterin detail wherein as one disabling operation Q3 is fired after the inputof the fourth character of a message (assuming message composition offour members).

As part of the operation just described there is provided a path fromthe gate circuit of Q2 through a current limiting resistor R9 and anisolating diode D1 to the START terminal of a flipflop 58. The flip-flop58 may be considered as any standard unit adapted to be triggered toprovide one of two outputs of 10" supplied from 52. One output isassociated with an on condition which initiates a standard multivibrator60 to supply alternating pulses on the two output leads shown. The otheroutput of 58 serves to turn 60 off and thereby stop the supply of pulsesoutput therefrom. The output of 60 is connected to a driver 62 capableof supplying properly timed advance and prime pulses to the register 56to advance or shift the message therein. Assuming the register 56 to becomprised of multiaperture cores coupled in accordance with the MAD-Rtechnique, the driver 62 is preferably that of the above-mentionedDormer application.

When Q2 fires a pulse is produced which starts 58, 60 and 62 to advancethe first character set into 56 out of the first five stages or coresalong the register to make room for the second character of the messageto be stored. therein.

Advance of the characters set into 56 is controlled as follows. At theend of each transmission, by means to be described, the sixth stage isset (the remaining stages or cores being cleared out to provide the tagbit heretofore mentioned). This tag bit always precedes a message andleads the first character along the register as 62 operates to advance.The eleventh stage of the register is made to include a dynamic outputwinding (numbered 11 in 56) leading to the gate of an SCR, Q4 (FIG. 5B).When the tag bit is input to stage ll the output winding will produce apulse to the gate of Q4 causing it to fire and latch on supplied bycurrent through limiting resistor R10 from other control circuitry, inturn supplied by the 40" lead of 52. When Q4 fires it cuts ofi' Q1 aspreviously mentioned and provides a pulse from its cathode through anisolating diode D2 and capacitor C3 to a lead going to the STOP terminalof 58. Resistor R11 couples DC components of this pulse to ground. Thepulse produced when Q4 goes on thus cuts off 58, 60 and 62 to stop theadvance of the message. This leaves the tag bit in stage 1 l and thestored S-bits (two set and three clear conditions) in the stagesnumbered 6-10. This also leaves the first five stages clear for theinput of the next or second character of the message.

Assuming now that the switch for the second character 3 is closed, thecircuit will operate as just described to set the stages 3 and 4,leaving the stages 1, 2 and 5 clear. See FIG. 4. Flip-flop 58 will againbe energized by O2 to advance the stored message. The tag bit will movefrom stage 1 l to stage 16. Another dynamic output winding on stage 16leads to the gate of SCR O5 to cause it to fire and hold on in themanner described relative to 04. This produces a pulse to the STOP leadof 58.

The next or third character 7 set into 56 causes an advance until thetag bit reaches stage 21 to provide an output to gate Q6 on which, asdescribed, serves to again stop 58 and further advance. The last orfourth character is then input into the first five stages and then themessage is advanced until the tag bit enters stage 26 to fire Q7 andagain stop transfer. At this time the tag bit is in stage 26 and thefour characters of the message are in stages 625.

When Q7 is gated on a lead from its cathode circuit carries the ensuingvoltage transient through coupling capacitor C4 to gate of an SCR Q8.This gates Q8 on to draw current through an auxiliary set winding (S5 in56) linking stage 5 to set such stage and provide a stop bit to completethe message stored in 56. The cathode of O8 is tied to ground and itsanode is connected through the winding S5 to draw current through anisolating diode D3 linking resistor R12 to the 40" supply lead.

The operation of the circuit to fire Q7 also serves to initiate messageoutput. When Q7 fires, the line leading from its cathode to resistor R13(in FIG. 5A) is placed at a voltage level to charge the capacitor C6.The charging time for C6 is made relatively short so that after afraction of a second the charge of C6 will fire unijunction transistorQ9. This delay is used to permit answering of multiple master encoders(by having different charging times in different encoders) and to assurecorrect operation of the circuit to prevent output if the line is busy.Conduction of Q9 will produce a pulse through isolating diode D4 to theSTART terminal of 58 causing 58, 60 and 62 to advance the message storedin 56 out of the register. The output winding labeled OUT is connectedto input the message serially to a pulse stretcher 64.

The unit 64 may be considered as standard, having the required functionof translating the dynamic output from the stages (which if cores, wouldbe a few microseconds in length) into pulses of lengths suitable for thetype of waveform heretofore described.

During this time a capacitor C7 is also being charged through a pathincluding isolating diode D5 and charging resistor R14 connected by alead to the cathode of Q7. The charging rate of C7 is relatively long(about 1 second) to permit the operation of 64 and the translator toaccommodate the complete message which is then transmitted. When C7 issufficiently charged it operates to fire a unijunction transistor Q10drawing current from limiting resistor R16 and the 10 supply from 52.

The output of Q10 is connected to the gate of an SCR Q11, which iscaused to fire and pull the base of the Darlington transistors Q12 and013 to ground and effect cutoff. The transistor Q12 and Q13 are suppliedby the 40' lead from 52 to provide the holding current to the SCRsQ4-Q'7. When Q12 and Q13 cutoff, Q4-Q7 also cut off and Q1 goes back onto cut on lamp LA1 and indicate that the circuit is ready for the nextmessage.

When Q11 is cut on its anode circuit is pulled to ground to in turnsupply a pulse on the lead connected to 64 at the end of the message.This reestablishes the initial circuit condition and prevents anerroneous output to the translators. When Q11 comes on, C5 dischargesthrough D3 and the winding designated S6 which operates to clear all ofthe stages except 6, which is set with the tag bit for the next messageto be encoded. The inductor L2 serves to shape this pulse. Q11 remainson until C5 is discharged and then cuts off due to a lack of holdingcurrent. When Q11 goes off, Q12 and Q13 come on to reestablish the anodesupply to Q4-Q7 which are then off, but prepared for the next message.

Going back to the operation of Q7, when it is gated on by the input ofthe fourth character, the lead from its cathode extends over to the baseof Q3 through R8. When Q6 goes on this operates to disable Q3 and theassociated circuit to prevent its operation to set the register withmessage characters.

If the transmitter is busy at the time a message is initiated byoperation of 54, the circuit including Q2 will also be disabled. This isaccomplished by a connection from the transmitter to the lead labeledLine to the left of FIG. A under 54. This lead is coupled through adiode D6 to the base of an NPN transistor Q15 and through the emitter of015 to the voltage divider comprised of resistors R18 and R19 to thebase of NPN transistor Q16, both of which are normally off. The supplyis connected to the emitter of Q17, which has its collector tied toground through R22. The collector of 015 is also tied to the 10" supplylead from 52, which is extended through a limiting resistor R20 to thecollector ofQl6.

The base ofQ17 is coupled through a speedup capacitor C9 and a resistorR2] to the collector of Q16, which is connected through an isolatingdiode D7 to the emitter ofQ9. The collector ofQl7 is connected to a leadgoing to the diode D8 to provide a back bias. The emitter of Q16 issuitably connected through the diode D9 to ground.

A diode D10 is connected in circuit with its anode to the anode of D8and its cathode to the anode of D7 through R13.

With this circuit, if the line lead is busy it will experience positiveand negative levels of voltage as the waveform rises and falls. Thepositive levels will gate Q15, Q16 and Q17 on to draw current from the10 supply. This will drop the voltage of the line leading to D7 down toa low value. This forward biases D7 to cause C6 to dump its charge sothat it cannot fire Q9. When Q is off (no line signal) D7 is back biasedto permit C6 to charge as previously described. When the line lead isbusy the positive excursions of the waveform voltage cause Q17 to fire.This back biases D8, which permits D10 to be back biased by input of thefourth character of the message when Q7 tires to establish a voltagelevel connected to the cathode of D10. This causes the common pointconnected to the anodes of D8 and D10 to experience a rise in voltagewhich couples through C12 to the cathode of Q14, permitting C7 to chargethrough Q14 to ground. The diodes D8 and D10 thus serve to disableencoding if the line is busy or if the fourth character has been setinto the register.

In the foregoing manner the invention system is carried out toautomatically encode a message in the form shown in FIG. 4.

DETAILED DECODER DESCRIPTION FIGS. 6 and 7 show two magnetic core arraysset up to decode the messages 5371 and 5373 shown in FIG. 4 to provide adetect output. Each array is wired to respond to the L and I; pulsesheretofore discussed and each array could therefore be associated with adifferent receiver station or with different functions at the samereceiver station. The leads shown represent drive windings connected inthe manner shown in FIG. 8 to drive in a selected pattern of 21multiaperture cores 0, and l,-20, arranged in the sequence of the bitpositions of the transmitted message. Each core may be a singlemultiaperture magnetic core, or integrated in some composite corestructure representing all of the cores. In either case there is foreach core a geometry defining major and minor apertures and associatedmajor and minor flux paths. The cores in FIG. 8 are shown as 70 toinclude a major aperture 72 and a minor aperture 74. In this particularembodiment the aperture 74 is a transmitting aperture. A number ofcoupling loops such as 76 link the cores in serial fashion to provide aserial transfer f magnetic remanence from core to core responsive to Land L drive pulses selectively applied through L and -L drive windings.These come from the pair of generators shown in FIG. 2. There is anadditional drive winding, not shown, which links all of the minorapertures of the cores in a sense to switch or prime flux in acounterclockwise sense relative to the minor apertures in the mannerdescribed in U.S. Pat. No. 3,125,747 mentioned above.

The leads from L and L are connected through turns denominated N,, N,and N, which link major or minor apertures of the cores in a selectedpattern. As will be apparent, the N, and N, windings link the coresthrough the major aperture and the turns N, link the cores through theminor transmitter apertures. The turns N, link only the 0;,core and arein a sense to drive such core to the set or 8 condition heretoforediscussed in terms of intelligence content. The set condition may betaken as that condition of magnetic remanence wherein all of theremanent flux is in a counterclockwise direction. The N, turns link thecores in a clearing sense and either drive or leave the cores so linkedin the clear or'C condition previously discussed. The clear conditionhas all of the remanent flux oriented in a clockwise direction. The N,turns link the core minor apertures in a sense so as to switch flux in aclockwise sense about the minor aperture 74. Additionally included withrespect to the circuits of FIGS. 6, 7 and 8, but not shown, is a windinglinking all of the cores O and l,20 with N turns so as to clear out theentire chain of cores.

Linking the last core 20, is a coupling loop denominated output whichgoes to the indicator or function device heretofore mentioned.

As mentioned, prior to the receipt of any message, all of the cores 0,and l,-20, are placed in the C condition effected by the application ofa clearing pulse at some period of time after the end of the lastmessage. This is shown relative to the time and sequence of the messagesin FIG. 4 on the line labeled clear. Prior to the receipt of a messagethe L generator 28 produces pulses through the 1 line. This effects notransfer function, since all of the windings associated therewith are N,or N, turns and all of the cores are then in the clear condition. As thefirst bit of each message comes in the L line is energized with an Lpulse. This operates on the N, turns linking 0, to drive the core to theset condition. The first pulse operates on the remaining cores againthrough only N turns and N, turns, and since the remainder of the coresare already in the cleared condition no system function results. The N,turns linking core 0, are made sufficient relative to the N, turnslinking the same core to provide an MMF overriding the MMF due to N, sothat the core 01,. is completely set. Reference may be made to FIG. 9 toshow the initial states of the cores and then the states of the coresfollowing the receipt of each of the L and L pulse associated with thefirst message. As can be seen, following the receipt of the L and Lpulse associated with the first message. As can be seen, following thereceipt of the tag level pulse the core 0, is set and theremaining'cores are cleared. The next pulse in accordance with the firstmessage is again an L pulse applied to the L line shown in the drivecircuit. This will again set core 0, The application of the L pulse willoperate differently on core 1, with respect to the N, turns at thistime, due to the priming operation which will have switched the set fluxabout aperture 74 so that the MMF applied via the N turns will cause atransfer of flux via coupling loop 76 to the core numbered 1, to setsuch core, thus transferring the set condition t o core number 1,. Thisis shown in FIG. 9. The next pulse is L and as is indicated from theFIG. 9, it results in a transfer of a set condition stored in core I, tothe core number 2,. This is again due to the N, turns linking core 1,,which, because of the priming function w l contain flux in a propersense to be switched by such turns to transfer the set condition to corenumber 2,. The next pulse is again a L pulse and it will effect atransfer of the set condition state stored in core number 2,. to corenumber 3,. It should be noted that certain of the cores preceding thecore number 3, will be set or partially cleared out by the pulses on N,,N, and N The important thing, however, is the advance of the setcondition along the cores. If the next pulse is a proper pulse inaccordance with the code, which would be an L pulse, the set conditionwill be transferred to core number 4,. If the remaining pulses areproper in accordance with the assigned code the set condition will becontinuously advanced to core number 20, and an output will be providedon the output loop connected thereto to provide an indication or controlfunction heretofore described.

Relative to the foregoing description of a successful advance, it willbe observed that the logic utilized with the detector circuits of FIGS.6, 7 and 8 are one of selectively omitting the N -turns from successivecores in accordance with the particular code assigned. For example, thefirst pulse in accordance with the code shown in FIG. 4 after the tagpulse is an L pulse. It will be observed that the N, turns associatedwith the L leads are omitted from core number 1,. In a similar mannerthe third and fourth pulses in accordance with the code are both T.pulses and the N, turns associated with the L lead are omitted from thecores numbered 2, and 3,. The L and L pulses are, however, applied toeach core 0, and I, through 20,. via the N turns which link all coresand are in series with the L andI: leads. A successful transfer is thendependent upon whether or not there is an MMF developed in the receivercore, which will swamp out or block the successful transfer initiated bythe N turns on the preceding core. To explain this more completely,assume that the first pulse of the message (after the tag pulse) isincorrect, which would mean that it would be a L pulse rather than an Lpulse, as shown in FIG. 4. The L pulse would tend to drive core 0,through the N, turns to transfer its set state to core number 1,. The Lpulse would, however, drive core number 1, through the N, turns in aclearing sense to block the receipt of the set state and thus prevent asuccessful propogation. If all the remaining code bits were correct thelast core would still be in the clear condition at the end of themessage and no output would occur. In the same manner an incorrect bitanywhere in the message would cause a failure of transfer and precludeany output.

The second message of FIG. 4, 5373, necessitates a change in the wiringpattern of the decoder. This is shown for comparison in FIG. 7 by thechange in the N, windings of the last five cores. In this regard and asa significant aspect of the invention, circuit changes to facilitatereceipt of different codes are accomplished by the structure shown inFIGS. 10, 11 and 12. The unit 80 represents a receiver station set up toreceive the code 5371. This assignment is accomplished by code plugs 82which each are inserted into the face of 80 to engage pin members 84shown in FIG. 11, which are connected to core windings in the decoder.Each pairof pins is made to connect the ends of a selected core clearingwinding N,. This is shown in FIG. 8 by the points P as to cores 1, and2,. The windings installed on the cores are fixed and the windings tothe pins are fixed. Each of the character positions include an array ofpins connected to provide clearing inputs to the numbered cores 1,.,,,The N, input to core and the N, turns are hard wired into the register.

Each plug 82 includes a body 82a formed of plastic material having therelated number printed on the face, as indicated in FIG. 10. Attached tothe body is a plate 82b, as shown in FIG. 11, carrying a number ofreceptacles 82c aligned to mate with the pins 84. The pins are connectedby conductive paths 82d (printed circuit, solder or wires) in patternsto define the interconnections necessary to define the choice of coresfor the character. As previously mentioned, code assignment is achievedby not driving a given core with N turns. Thus, in FIG. 8, the cores 1,,4,, 5, are not driven by N, from L and the cores 2,, 3, are not drivenby N, from L. In FIG. 8 the paths 82d form the connections in the L leada to b, b to c, (shorting out the N, winding from L on core 1,) c to d,e tofand so on along the array ofcores.

As the L lead the paths 82d connect 3 to h, h to i, itoj,j to k and soon down the core array.

In this manner a given decoder design can be constructed for all codes,the particular code assignment being made by selection of a numberedplug. The decoder for 80, set up for 5371, would then detect 1735 if theplugs were reversed from that shown. As can be discerned, considerableeconomies are derived by making all decoders identical, except for therelatively inexpensive code plugs.

Referring now to FIG. 13, there is shown in detail a circuit 100 for thedecoder of the system of the invention. The circuit is supplied by a 12DC supply regulated to about volts by a standard C regulator 102, whichis also used to supply the receiver of the system. The output of 102 isthen connected in a DC to DC converter 104, which converts the 10 voltsto about 40 volts used to power the magnetic driver 106 of the circuit.The driver 106 is preferably of the type disclosed in the Dormerapplication previously mentioned. The driver 106 is connected to supplyproperly timed and shaped advance and prime pulses to the magnetic coresand windings schematically represented in unit 108. The winding schemeis shown in detail in the above-mentioned Sweeney et al. application.Also connected to the magnetic unit is a reset circuit including anormally closed switch 108 supplied by +10 and in series with anindicator lamp LA2 adapted to be driven by an SCR Q20, which is normallyoff. The lamp LAZ serves the function mentioned relative to FIG. 3 ofindicating the successful detection of a received code. As alsomentioned previously, this may serve to indicate that the station isbeing called or paged, or it may constitute a control function. The SCRQ20 has its gate connected to the output of the magnetic decoder unit(the last core) and is triggered on by such output to hold on, suppliedfrom the 10" supply from 104. When Q20 is fired the resulting voltagedeveloped across R60 is caused to gate a further SCR Q30 on to drawholding current from 104 through the coil of a loudspeaker LS. Thisoutput from 104 is preferably made oscillatory, about 1.2 k.c.p.s, toprovide an audible tone from LS to supplement the visual indication ofLA2.

The three leads from 106 are advance and prime drive leads connected tothe various turns linking the cores of 108.

In accordance with the operation of the decoder heretofore described, Land L pulses are generated in a pattern to cause the successful advanceof a set condition from the core through the remaining cores l,20,. TheL andL pulses are developed by selectively gating one of the SCRs Q21and Q22 on to close a path to ground from the magnetic driver 106. Asexplained in the Dormer application, the pulse for the advance, or L andL, circuits, including turns N and N, is derived by discharging acapacitor such as C15 through a pulse shaping network including L3. Thecapacitor recharges through the priming circuit, turns N priming thecores for the next advance L or L pulse.

There is an additional clearing path shown connected to an SCR Q23 andto the 40 volt supply through a charging network. This network includesa coupling diode D15 and resistor R30, a charging resistor R31,capacitor Cl6and a pulse shaping indicator L4. Capacitor C16 is chargedfrom the supply and discharged when Q23 is fired by a control pulsegenerated elsewhere in the circuit. When Q23 fires the associated N,turns clear out all the cores of the decoder. This occurs betweenmessages as shown in FIG. 4 on the line labeled clear.

Referring now to the data input side of circuit 100, the waveform ofFIG. 4 comprising the transmitted message is input through a leadincluding a decoupling circuit comprised of a capacitor C17, a capacitorC18 and an inductor L5. This circuit effectively grounds high frequencycomponents which may be passed on from the receiver. The resulting inputis then essentially the waveform transmitted in terms of ti e presenceor absence of a voltage level. In practice the waveform generated as aninput to the transmitter will appear as in FIG. 4 or in part in FIG. MA.

This waveform may experience some degradation due to transmitter rangeor doppler effect, if the medium of transmission is radio. This is shownby the waveform 14B. Alternatively, the time period wherein there isnolevel may experience some transient like that shown in FIG. 14D. Thisphenomena occurs as ringing in land line transmission. The circuit isadapted to prevent a failure of response due to the type of degradationevidenced by FIG. 14b and to prevent a wrong call response due to thespurious pulse shown in FIG. MD.

This is accomplished by a number of circuit features which will now bemade apparent. The filtered input from the data line is fed to the baseof a transistor Q23 which serves an an emitter follower. The collectorof Q23 is supplied from the 10" supply of 102 and its emitter isconnected through a voltage divider comprised of R32 and R33 to the baseof a transistor Q24. The resistors R32 and R33 are rated to hold Q24 offin the presence of low voltages developed by Q23, as for example,voltages below a 2 volt level. A resistor R34 is connected from the baseof Q23 to ground to bias the base against temperature efiects.

The transistor Q24, along with a transistor Q25, serves as a Schmidttrigger to restore the square wave shape of the input waveform from thatshown in FIG. 14A. The collectors of Q25 and Q24 are supplied inparallel from the supply, as shown, through limiting resistances R35 andR36 and variable resistances R37 and R38. The emitters of 025 and 024are tied together to capacitor C19 and diode D16, which are in parallelto ground. This latter connection serves to set the triggering biaslevel necessary to fire Q24 and Q25. A capacitor C20 is connectedbetween the base of Q25 and the collector of Q24 to speed up theswitching action of the trigger resistor R39 maintains a DC level to 025from the supply.

A capacitor C21 is coupled to the collector circuit of Q24 through aresistor R40 and through a diode D17 and resistor R41 in parallel withR40. The capacitor C21 is also coupled to the emitter of a unijunctiontransistor Q26 having one electrode connected through a limitingresistor R42 to the 10" supply and its other electrode connected througha signal developing resistor R43 back to the other side of C21 and toground. Additional unijunction transistors Q27 and Q28 are in parallelwith 026 with respect to the supply and to ground. The transistor Q27has its emitter connected through a variable resistor R50 back to theresistor R37 in the collector circuit of Q24. The other transistor Q28has a similar connection to the collector of Q25. The emitter of Q27 isalso connected to a capacitor C22 and the emitter of Q28 is similarlyconnected to a capacitor C23. 4

The other electrodes of O26, Q27 and Q28 are each respectively connectedto its gates of O21, Q22, and Q23 through a resistor such as R49 shownrelative to Q26.

As previously mentioned relative to FIG. 3, when no message is beingtransmitted the decoder is continuously supplied with L pulses. This isachieved as follows. Capacitor C22 draws a charging current through R45,R50 and R35 from the 10" supply to raise the voltage to the emitter ofQ27 until it goes on to discharge C22. This discharge presents a gatingpulse to the gate of Q22 causing it to fire discharging C through the Llead. As soon as C22 is drained Q27 goes off. Q22 will go off when C15is drained to permit C15 to recharge. This operation repeats to producea train of L pulses to the decoder as long as the L condition exists andthere is no input level to the circuit. The charging period of C22 ismade to be about 22 milliseconds. During this time Q23 and Q24 are heldoff by the base path to ground. When 024 is off the 10 supply (throughthe path R35, R37 and R40) serves to charge C21, which is made to have arelatively long charging time (about 130 milliseconds). As C21approaches its charged condition it biases the emitter of 026 to causeit to go on temporarily providing a gate pulse to fire Q23 and develop aclear pulse through the decoder. Capacitor C21 will again charge and theforegoing will repeat as long as the 1: condition remains. The clearpulse function has been previously mentioned.

During the L input condition Q25 is on supplied from the 10 supply asshown. There is a lead from the positive side of R36 to the emittercircuit of 028 which leads to C23. This places a reduced chargingvoltage on C23 which is adjusted by R38 to cause it to charge to abouthalf its full level. The capacitor C22 is similarly supplied via a leadto the positive side of R35. During the L condition Q24 is off and R50is adjusted to provide the charging period heretofore mentioned.

When L comes on the half charge on C23 will cause Q28 to come on in lesstime than if C23 were drained. This period is made to be about 11milliseconds. When the L condition is present C22 is brought to halfcharge by the connection through R50 to R35, 024 being then on and R37being adjusted to provide the proper charging voltage.

In summary, the capacitors C22 and C23 each first charge to cause Q27and 028 to come on about I 1 milliseconds after the Schmidt triggerswitches and thereafter required full time to charge. This causes theSCR's Q21 and Q22 to produce & and L pulses spaced 11 milliseconds afterthe L and L waveform conditions occur and thereafter to produce pulsesspaced 22 milliseconds apart.

When the waveform representing the message is input to the first portionis always L. This cuts on Q23, which cuts on Q24 and cuts off Q25. WhenQ24 comes on the current charging C21 is drawn off to disable Q26 andQ23 and prevent the clearing operation. When Q24 comes on C23 chargesand gates 028 to fire 021. As mentioned, Q24 in conducting prevents C22from charging sufficiently to cause Q27 to come on, thus disabling the Lside from firing as long as the L side is on. When the voltage level ofthe waveform goes off, back to L, Q23 goes off, Q24 goes off and Q25comes on to reestablish the circuit. The waveform of FIG. 4 will, in themanner outlined, drive circuit 100 to produce an output from 108. Thelast bit of all messages is made to return the decoder to L, whichassures preparation for the next message.

Referring back to FIGS. 14A-E the delay of 11 or so milliseconds due tothe operation of C22 and C23 also operate to reduce spurious inputs.FIG. 148 shows a badly distorted L pulse. FIG. 14C shows the operationof C23 in charging to cut on Q28 responsive to the operation of 024 andQ25. As shown by the line above 0", C24 is partially charged. As soon asthe input level exceeds the threshold of Q23 it cuts 024 on and 025 offand C23 charges to the threshold of Q28. 1f the spurious pulse of FIG.14D occurs 023 will come on to cause Q24 to come on and Q25 to go off,but C23 will follow such and as soon as the transient drops to cut Q24off the charge on C23 will drop to the half charge level.

Having now disclosed general and specific embodiments of our selectivesignalling system to enable its practice, the following claims areincluded to define what is asserted as the invention.

We claim:

1. A circuit for generating a message code comprised of a series of setand clear states made up of a series of distinct subseries of set andclear states comprising a register including a series of bistable stagescapable of storing set and clear states, said stages being connected forserial transfer, first input means to inject a subseries in saidregister, translating means responsive to the output of said drive meansoperable to on and off conditions with said on condition effecting arepeated drive to said stages to transfer the states stored therein,first control means responsive to each operation of said first inputmeans to actuate said drive means to the on condition and second controlmeans to actuate said drive means to the off condition, second inputmeans connected to a first subseries of stages in the first portion ofsaid register, third input means connected to a stage adjacent to thefirst portion of said register, the said third input means operating toinject a tag bit in said register prior to the input of a message code,first output means connected to the first stage of each successive subsc'ies of stages after the second and energized by the input of a setstate, said first output means being connected to operate said secondcontrol means whereby following each input of a subseries the saidregister is caused to be driven to advance the subseries until said tagbit energizes the nest output means whereupon transfer is halted untilthe next input.

2. The encoder of claim 1 including means to input into said register atag character leading the first message character and a stop characterfollowing the last character defining the calling code.

3. The encoder of claim 1 wherein said input means is operable to inputan even number of set states for each character.

4. The encoder of claim 3 wherein the said input means is operable toset an even number of set states for each character and the means toinput the tag and stop characters is connected to set stages definingsuch characters in an identical sense.

5. A decoder for use with a selective signalling system including avoltage source adapted to be connected to drive first and second pulsegenerators in response to an on-off voltage waveform representing acalling code, a plurality of bistable stages connected in series to bedriven by said generators with each stage being capable of being drivento a set or clear condition, the said stages being connected to saidgenerators in a pattern to provide a serial comparison of pulsesproduced by said generators to effect an advance of a set conditionalong said stages for one pattern and block the advance of a setcondition for all other patterns whereby to provide a detect outputsignal for a proper calling code and no output signal for impropercodes, means for clearing out said stages prior to the receipt of amessage and means for setting the first stage at the receipt of acalling code, means responsive to said waveform to connect said sourceto drive one generator each time the voltage waveform goes on and todrive the other generator each time the voltage waveform goes offwhereby to energize one or the other of said generators to provide pulseinputs to said stages in a given pattern, wherein there is includedmeans responsive to the absence of a voltage level input to said decoderto drive the generator associated with the absence of a voltage levelcontinuously between calling codes, wherein the said means for clearingout said stages includes means operable a given period of time aftersaid voltage level has been absent to effect the clearing of said stagesprior to the receipt of a calling code.

6. The decoder of claim wherein each said stage includes an inputwinding to drive said stage to a clear condition and the said patternconnection to said generators is made by a series of connectors linkingcertain of said stages of said generators to accomplish said pattern.

7. The decoder of claim 5 wherein there is included a separate connectormeans for connecting said stages to said generator in said pattern toprovide said serial comparison of the pattern of pulses provided by saidgenerators.

8. The decoder of claim 5 wherein there is included as part of suchsource a filter responsive to the presence of a tone input thereto andsaid on-off waveform is comprised of the presence of absence of saidtone.

9. The decoder of claim 5 wherein there is included as a part of saidsource first and second filters each responsive to first and secondtones and said on-off voltage waveform is comprised of the first andsecond tones representing on and off conditions.

10. In a selective signalling system the combination comprising anencoder for providing a calling code and a plurality of decoders, onefor each calling code, the encoder including means to register a seriesof numbers as a given calling code and means responsive to registrationof a complete calling code to translate said numbers into a waveform ofgiven time duration comprised of a series of on or off voltageconditions, each decoder generator means responsive to said waveform totranslate said condition into a series of on-off pulses, a register ofbistable state stages coupled for serial transfer, means in each decoderresponsive to said pulses to apply an advance drive to said stages toadvance a given state therealong, and means in each register to effect acomparison of each pulse of said sequence with the sequence assigned tosaid decoder to permit the advance of a given state therealong toproduce an output signal if said sequence is correct whereby eachdecoder or said system responds to said waveform but only one decoderfurther produces an output signal, wherein there is included meansresponsive to the absence of a voltage level input to said decoder todrive the generator associated with the absence of a voltage levelcontinuously between calling codes, wherein the decoder includes meansfor clearing out said register a given period after the cessation of anon voltage condition.

11. The system of claim 10 wherein each decoder includes a plurality ofconnectors whereby to permit a change in the sequence of compared pulsesto effectively change the code assigned to said decoder.

37 3 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3,596,181 Dated July 27, 1971 Inventor(s) EDWARD CAMP DOWLING ET AL Itis certified that error appears in the above-identified patent and thatsaid Letters Patent are hereby corrected as shown below:

fm Column 16, claim 1, line L Z, after "said" should be inserted shiftregister to produce an on and off waveform,

Same column, same claim, line 58, "nest" should be next Column 18, claim8, line 2, "of" should be -R m or Same column, claim 10, line 15, after"decoder" should be inserted including Signed and sealed this 11th dayof January 1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Air-testing; Officer ActingCommissioner of Patents

1. A circuit for generating a message code comprised of a series of setand clear states made up of a series of distinct subseries of set andclear states comprising a register including a series of bistable stagescapable of storing Set and clear states, said stages being connected forserial transfer, first input means to inject a subseries in saidregister, translating means responsive to the output of said drive meansoperable to on and off conditions with said on condition effecting arepeated drive to said stages to transfer the states stored therein,first control means responsive to each operation of said first inputmeans to actuate said drive means to the on condition and second controlmeans to actuate said drive means to the off condition, second inputmeans connected to a first subseries of stages in the first portion ofsaid register, third input means connected to a stage adjacent to thefirst portion of said register, the said third input means operating toinject a tag bit in said register prior to the input of a message code,first output means connected to the first stage of each successivesubseries of stages after the second and energized by the input of a setstate, said first output means being connected to operate said secondcontrol means whereby following each input of a subseries the saidregister is caused to be driven to advance the subseries until said tagbit energizes the nest output means whereupon transfer is halted untilthe next input.
 2. The encoder of claim 1 including means to input intosaid register a tag character leading the first message character and astop character following the last character defining the calling code.3. The encoder of claim 1 wherein said input means is operable to inputan even number of set states for each character.
 4. The encoder of claim3 wherein the said input means is operable to set an even number of setstates for each character and the means to input the tag and stopcharacters is connected to set stages defining such characters in anidentical sense.
 5. A decoder for use with a selective signalling systemincluding a voltage source adapted to be connected to drive first andsecond pulse generators in response to an on-off voltage waveformrepresenting a calling code, a plurality of bistable stages connected inseries to be driven by said generators with each stage being capable ofbeing driven to a set or clear condition, the said stages beingconnected to said generators in a pattern to provide a serial comparisonof pulses produced by said generators to effect an advance of a setcondition along said stages for one pattern and block the advance of aset condition for all other patterns whereby to provide a detect outputsignal for a proper calling code and no output signal for impropercodes, means for clearing out said stages prior to the receipt of amessage and means for setting the first stage at the receipt of acalling code, means responsive to said waveform to connect said sourceto drive one generator each time the voltage waveform goes on and todrive the other generator each time the voltage waveform goes offwhereby to energize one or the other of said generators to provide pulseinputs to said stages in a given pattern, wherein there is includedmeans responsive to the absence of a voltage level input to said decoderto drive the generator associated with the absence of a voltage levelcontinuously between calling codes, wherein the said means for clearingout said stages includes means operable a given period of time aftersaid voltage level has been absent to effect the clearing of said stagesprior to the receipt of a calling code.
 6. The decoder of claim 5wherein each said stage includes an input winding to drive said stage toa clear condition and the said pattern connection to said generators ismade by a series of connectors linking certain of said stages of saidgenerators to accomplish said pattern.
 7. The decoder of claim 5 whereinthere is included a separate connector means for connecting said stagesto said generator in said pattern to provide said serial comparison ofthe pattern of pulses provided by said generators.
 8. The decoder ofclaim 5 wherein there is included aS part of such source a filterresponsive to the presence of a tone input thereto and said on-offwaveform is comprised of the presence of absence of said tone.
 9. Thedecoder of claim 5 wherein there is included as a part of said sourcefirst and second filters each responsive to first and second tones andsaid on-off voltage waveform is comprised of the first and second tonesrepresenting on and off conditions.
 10. In a selective signalling systemthe combination comprising an encoder for providing a calling code and aplurality of decoders, one for each calling code, the encoder includingmeans to register a series of numbers as a given calling code and meansresponsive to registration of a complete calling code to translate saidnumbers into a waveform of given time duration comprised of a series ofon or off voltage conditions, each decoder generator means responsive tosaid waveform to translate said condition into a series of on-offpulses, a register of bistable state stages coupled for serial transfer,means in each decoder responsive to said pulses to apply an advancedrive to said stages to advance a given state therealong, and means ineach register to effect a comparison of each pulse of said sequence withthe sequence assigned to said decoder to permit the advance of a givenstate therealong to produce an output signal if said sequence is correctwhereby each decoder or said system responds to said waveform but onlyone decoder further produces an output signal, wherein there is includedmeans responsive to the absence of a voltage level input to said decoderto drive the generator associated with the absence of a voltage levelcontinuously between calling codes, wherein the decoder includes meansfor clearing out said register a given period after the cessation of anon voltage condition.
 11. The system of claim 10 wherein each decoderincludes a plurality of connectors whereby to permit a change in thesequence of compared pulses to effectively change the code assigned tosaid decoder.